/*
 * T3.c
 *
 *
 * Timer 3A is a 1 shot timer, Timer 3B is set up for input edge timing.
 *
 *
 *
 *  Created on: 07/03/2013
 *      Author: Bowmer
 */

#include "inc/hw_types.h"
#include "inc/lm4f120h5qr.h"
#include "driverlib/gpio.h"

void Timer3_Pulse(void){

	/* Enable Timer A pulse */
	WTIMER3_CTL_R |= 0x00000001;
	GPIO_PORTD_DATA_R |= GPIO_PIN_2;

}

void Timer3_Init(void){

	//Enable PORTD peripheral
	SYSCTL_RCGCGPIO_R |= SYSCTL_RCGCGPIO_R3;							//Add PORTD to enabled peripherals

	//Configure PORTD
	GPIO_PORTD_DIR_R = (GPIO_PORTD_DIR_R & ~GPIO_PIN_3)|GPIO_PIN_2;		//Pin 3 is an input, 2 is an output. Maintain other bits
	GPIO_PORTD_AFSEL_R |= GPIO_PIN_3;						            //Alternate function on pin 3
	GPIO_PORTD_PCTL_R |= GPIO_PCTL_PD3_WT3CCP1;	                        //Alternate function is Timer3 CCP
	GPIO_PORTD_DEN_R |= (GPIO_PIN_2|GPIO_PIN_3);						//Digital Enable


	/**********************/
    /*  Configure TIMER3  */
	/**********************/


	/* Enable Wide TIMER3 peripheral */
	SYSCTL_RCGCWTIMER_R |= SYSCTL_RCGCWTIMER_R3;


	/* Disable Timers A and B */
	WTIMER3_CTL_R &= ~(0x00000101);
	/* 32 bit timer */
	WTIMER3_CFG_R = 0x00000004;
	/* Configure as Match Interrupt Enable, Count Up, One Shot */
	WTIMER3_TAMR_R = 0x00000031;
	/* Configure as Count Up, Input Edge timing */
	WTIMER3_TBMR_R = 0x00000017;
	/* Timer1B generates events on both rising and falling edges */
	WTIMER3_CTL_R |= 0x00000400;

	/* Invert the output on Timer1A-PWM */
	WTIMER3_CTL_R |= 0x0000040;

	/* Timer1B Event, 1A Overflow Interrupts Enabled */
	WTIMER3_IMR_R = 0x00000401;

	/* Enable Wide Timer2A,B in the NVIC */
	NVIC_EN3_R |= (NVIC_EN0_INT4 | NVIC_EN0_INT5);


	/* 48 bit match value - TAPR contains bits 32-47, TAMATCHR contains bits 0-31 */
	/* Given fCPU 40MHz, need a high time of 300us */
	/* 40E6*300E-6 = 0d00012000 = 0x00002EE0*/
	WTIMER3_TAPR_R = 0x0000;
	WTIMER3_TAILR_R = 0x2EE0;

	WTIMER3_TBPR_R = 0xFFFF;
	WTIMER3_TBILR_R = 0xFFFFFFFF;


	/* Enable TimerB (timerA gets triggered by request) */
	WTIMER3_CTL_R |= 0x00000100;

}


